In a digital processor such as a graphics processing unit of a computer system, multiply-adders are commonly used to implement the calculation of, for example, a plane equation O=A+Adx*DX+Ady*DY, where O, A, Adx and Ady are floating points, DX and DY are integers, and the resulting value O repeatedly replaces the value A in subsequent operations to obtain new values O. Thus, it can be realized thatA[1]=A[0]+Adx*DX[0]+Ady*DY[0];A[2]=A[1]+Adx*DX[1]+Ady*DY[1];A[n]=A[n−1]+Adx*DX[n−1]+Ady*DY[n−1],where n is a natural number.
Please refer to FIG. 1 that a block functional block diagram illustrating a conventional accumulating operator for operating the plane equation A[n]=A[n−1]+Adx*DX[n−1]+Ady*DY[n−1]. By this accumulator, a series of output values A[n] can be obtained with floating points A[0], Adx and Ady and input integers DX[0] and DY[0] inputted from the external. The floating point A[0] selected via a multiplexer 11 is first transferred to a register 12, and subsequently operated in an adder 103 of a multiply-adder 10 with the floating points Adx and Ady which have been operated in multipliers 101 and 102 of the multiply-adder 10, respectively, to obtain an output floating point A[1]. The output floating point A[1] then substitutes for the previously inputted floating point A[0] to be operated with input integers DX[1] and DY[1] in the multiply-adder 10 to obtain an output floating point A[2]. Likewise, the output floating point A[2] and integers DX[2] and DY[2] are inputted to obtain an output floating point A[3]. In this manner, a series of output floating points A[1], A[2], A[3], . . . , can be obtained.
Typical floating point notation used in a computer system is based on a binary system. For example, the floating point notation of a value 18.75 in a decimal system is (10010.11)2 in the binary system, or expressed as 1.00101*24. After normalization, the single precision floating point is recorded as the following in a storage media:
wherein the bit in the first column indicates the sign, i.e. “0” for positive or “1” for negative; the bit combination in the second column indicates the biased exponent “4” on the condition that (01111111) represents “0”; and the bit combination in the third column indicates the mantissa.
When executing addition operation, members of the additive group is required to have the same base and exponent. In other words, the bit combinations in the second columns of these members should be identical. Accordingly, for executing addition operation, one or more normalized values may need to be transformed so as to unify the exponent. Giving the expression “18.75+1.25” in the decimal system as an example, it will become “1.001011*24+1.01*20” in the computer system. For unifying the exponent, “1.001011*24+1.01*20” expressed as “1.00101100000000000000000*210000011-01111111+1.01000000000000000000000*20111111-01111111” is transformed into “1.00101100000000000000000*2100000011-01111111+0.00010100000000000000000*2100000011-01111111”, which is thus equal to “1.01000000000000000000000*2100000011-0111111”. The operations are recorded as the following codes:

It is apparent from the above operations that if it is the small-value one to be transformed by biasing the exponent and shifting the mantissa backwards, the transformed value might become distorted because of the shift of the mantissa partly out of the range. This problem is particularly serious when the exponents differ a lot or the operations are repeatedly executed as in the multiply-adder 13 of FIG. 1.
The use of a multiply-adder of improved precision may solve this problem to a certain extent. An increased number of operating units and an enlarged size of memory, however, are required to achieve the high precision. Thus it will be cost-ineffective.